(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to forming dual damascene interconnects in a semiconductor substrate through the use of a novel method of etching.
(2) Description of the Related Art
In a damascene process, which is descried more fully below, grooves and holes are formed in an insulating material by etching which are then filled with metal. Metal in grooves form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure. The holes that interconnect metal lines at different levels in a semiconductor substrate are known as via holes. If the damascene structure forms the first level of metal, then the underlying holes may contact the substrate itself, in which case the holes are referred to as contact holes. Because the grooves and the holes in a damascene structure are filled with metal together, the interface resistance that would normally occur between a metal line that is deposited over a previously formed metal in the via or contact hole of the prior art method is eliminated. Hence, the damascene structure is a significant improvement over prior art.
In addition to the electrical resistance at metal interfaces, the conductivity of the metal interconnections themselves is becoming more and more significant especially in the ultra scale integrated (ULSI) technology of today. Thus, aluminum, which has been the material of choice since the early days of integrated circuit art, is becoming less attractive than other better conductors such as copper, gold, and silver. Copper is often preferred due to its low resistivity, high electromigration resistance and stress voiding resistance and is used as an interconnect material with the damascene process. However, the removal of excess copper over an overly filled damascene structure by the usual method of chemical mechanical polishing introduces problems associated with metal bridging. The bridging problem across the insulating material within which the damascene structure is formed is further exacerbated by the etching recipe used to form the damascene structure itself, as will be shown later. This problem is further compounded when low dielectric insulating materials are used. As is known in the art, low dielectrics are desired in order to keep capacitance between metal lines low, and especially small RC delays with the ULSI technology where line widths along with feature sizes of less than 0.35 micrometers (.mu.m) are being developed.
Commensurate with the shrinking line dimensions of the ULSI technology and the attendant chip size, the walls of the grooves formed in the damascene structure need to be vertical so as to conserve "real estate" or space on the chip. When the damascene structure is formed in low dielectric materials, new etching recipes are required which are disclosed later in this invention.
In a single damascene process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, the conductive hole openings are also formed in the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers.
In contrast, conventionally, the metal layers and the interconnecting layers are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate.
In the standard dual damascene process an insulating layer, (20), shown in FIG. 1a, is coated with a resist material, (30), which is exposed to a first mask with the image pattern of a hole opening (35') for either a contact or via hole, and the pattern is anisotropically etched, (35), in the upper half (20b) of the insulating layer. The hole depth in the insulating layer can be controlled by timed-etch. That is, the etch is stopped after a predetermined period of time. However, timed-etch is not always reliable. In order to have a better control on the depth of the hole, an etch-stop layer is also used. Thus, hole opening (35) in layer (20) stops at etch-stop layer (25) shown in FIG. 1a. The etchant is then modified to etch the hole pattern through the etch-stop layer and stop at the insulating layer below. After etching, patterned resist material (30) is removed, insulating layer (20) is coated with another resist material (40) and exposed to a second mask with image pattern of conductive lines (45') in alignment with hole openings (35). In anisotropically etching the openings for the conductive line in the upper half of the insulating material, the hole openings already present in the upper half are simultaneously etched in the lower half (20a) of the insulating material. After the etching is complete, both the hole openings and conductive line openings are filled with metal (50), and any excess material on the surface of the substrate is removed by chemical mechanical polishing.
In another approach for the dual damascene process, the conductive line openings, (45'), are etched first into the upper half of the insulating material, (20b), as shown in FIG. 2a, using an etch-stop layer (25). Resist material, (30), is next formed over the substrate, thus filling the line opening (45), and patterned with hole opening (35'), as shown in FIG. 2b. The hole pattern is then etched into the lower half (20a) of the insulating material, thus forming the dual damascene structure. Again, after the etching is complete, both the hole openings and conductive line openings are filled with metal (50), and any excess material on the surface of the substrate is removed by chemical mechanical polishing.
Other variations on the damascene interconnection process are disclosed in U.S. Pat. No. 5,614,765, and U.S. Pat. No. 5,686,354. In the former patent, Avanzino, et al., describe a self aligned via dual damascene where the conductive line openings and vias are filled with the same conductive material. In the latter, also Avanzino , et al., disclose another dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation using a thin protective via mask to form the via openings. Shoda in U.S. Pat. No. 5,529,953 proposes a method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure using selective deposition. Fiordalice, et al., on the other hand, disclose in U.S. Pat. No. 5,578,523 a method for forming inlaid interconnects in a semiconductor device. Another method for making metal contacts and interconnections concurrently is disclosed by Lee, et al., in U.S. Pat. No. 5,702,982. Jain, et al., use a dielectric tantalum nitride layer as an antireflective coating in a dual damascene structure in U.S. Pat. No. 5,741,626, while Zheng discloses in U.S. Pat. No. 5,705,849 an improved antifuse design by providing a structure comprising pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene connectors. Teong teaches an etch stop for a copper damascene process in U.S. Pat. No. 5,693,563. Shan, et al., disclose an adjustable DC bias control in a plasma reactor in U.S. Pat. No. 5,605,637.
The present invention discloses a novel method of etching a combination of low dielectric layers surrounding a copper dual damascene structure where the etching is accomplished in the same chamber in which the hard mask of the dual damascene structure is also etched.